//============================================================
//	COPYRIGHT(C) Innobeam
//	ALL RIGHTS RESERVED
//============================================================
//	Filename	: wheel_monitor.v rev 1.0
//	Created On	: 2019-05-31 11:58:36
//	Author		: HY.Xiao
//	Description	: 
//	Include		: 
//	Modification: 
//============================================================

`timescale 1ns/100ps

module wheel_monitor
(
	iRst_n,
	iClk,

	// to on chip adc
	oCmdValid, // channel number valid, control sampling frequency
	ovCmdCh, // channel number, control sampling object

	// form on chip adc
	iRailData_en, // rx data and rx channel enable
	ivRailCh, // rx channel number
	ivRailData, // rx adc data

	//output wheel data value
	ovwheel1, 
	ovwheel2, 
	ovwheel3
);

//============================================================
//	parameter
//============================================================
parameter
	CLK_DW = 15, 		// clock counter data width
	CLK_FLGA = 15'd25_000 - 1'b1, // The timekeeping mark of 1ms
	CH_DW = 2, 			// channel number data width
	CH_NUM = 4, 		// total number of channel, <= 2^CH_DW时
	RAIL_DW = 12, 		// power rail data width
	WHEEL_DW = 12;		// wheel data width
//============================================================
//	port
//============================================================
input	iRst_n;
input	iClk;

// to on chip adc
output					oCmdValid; 	// channel number valid, control sampling frequency
output	[ CH_DW-1: 0]	ovCmdCh; 	// channel number, control sampling object (channel)

// form on chip adc
input					iRailData_en; 	// rx data and rx channel enable
input	[ CH_DW-1: 0]	ivRailCh; 		// rx channel number
input	[ RAIL_DW-1: 0]	ivRailData; 	// rx adc data

// output wheel data value
output	[ WHEEL_DW-1: 0]ovwheel1;
output	[ WHEEL_DW-1: 0]ovwheel2;
output	[ WHEEL_DW-1: 0]ovwheel3;
//============================================================
//	localparam
//============================================================

//============================================================
//	signal
//============================================================
// to on chip adc
reg  [ CLK_DW - 1: 0] rvClk_cnt;
reg  oCmdValid;
reg  [ CH_DW - 1: 0] ovCmdCh;
// form on chip adc
reg	[ WHEEL_DW-1: 0]	ovwheel1;
reg	[ WHEEL_DW-1: 0]	ovwheel2;
reg	[ WHEEL_DW-1: 0]	ovwheel3;


//============================================================
//	module body
//============================================================

//==============================
// to on chip adc
//==============================

always @ (posedge iClk or negedge iRst_n)
	if (!iRst_n) begin
		rvClk_cnt <= {CLK_DW{1'b0}};
		end
	else if (rvClk_cnt >= CLK_FLGA) begin
		rvClk_cnt <= {CLK_DW{1'b0}};
		end
	else begin
		rvClk_cnt <= rvClk_cnt + 1'b1;
		end

always @ (posedge iClk or negedge iRst_n)
	if (!iRst_n) begin
		oCmdValid <= 1'b0;
		ovCmdCh <= {CH_DW{1'b0}};
		end
	else if (rvClk_cnt >= CLK_FLGA) begin
		oCmdValid <= 1'b1;
		if (ovCmdCh >= CH_NUM - 1'b1)
			ovCmdCh <= {CH_DW{1'b0}};
		else
			ovCmdCh <= ovCmdCh + 1'b1;
		end
	else begin
		oCmdValid <= 1'b0;
		ovCmdCh <= ovCmdCh;
		end

//==============================
// from on chip adc
//==============================
//generate wheel data value
always @ (posedge iClk or negedge iRst_n)
	if (!iRst_n) begin
		ovwheel1 <= {WHEEL_DW{1'b0}};
		ovwheel2 <= {WHEEL_DW{1'b0}};
		ovwheel3 <= {WHEEL_DW{1'b0}};
		end
	else if (iRailData_en & (ivRailCh == 2'b01)) begin
		ovwheel3 <= ivRailData;
		end
	else if (iRailData_en & (ivRailCh == 2'b10)) begin
		ovwheel1 <= ivRailData;
		end
	else if (iRailData_en & (ivRailCh == 2'b11)) begin
		ovwheel2 <= ivRailData;
		end
	else begin
		ovwheel1 <=ovwheel1;
		ovwheel2 <=ovwheel2;
		ovwheel3 <=ovwheel3;
		end

endmodule

